1. Technical Field
The present disclosure relates to a multilayer wiring board and a semiconductor device. More specifically, the present disclosure relates to a multilayer wiring board which is characterized by the geometry of wiring patterns and connection pads (or vias for connections to connection pads) formed on the respective wiring layers of the multilayer wiring board, as well as to a semiconductor device using the multilayer wiring board.
2. Related Art
In the related art, a semiconductor element is mounted on a wiring board by flip-chip bonding in the following manner. For example, as shown in FIG. 12, a semiconductor element 20 is mounted on a wiring board 10 such that connection pads 12 that are provided in a semiconductor element mounting area of the wiring board 10 and bumps 22 that are formed as electrode terminals of the semiconductor element 20 are aligned with respect to each other. To this ends the connection pads 12 which are provided in the semiconductor element mounting area of the wiring board 10 have the same plan-view geometry as the bumps (electrodes) 22 of the semiconductor element 20.
In semiconductor elements, with the increase in the number of inputs and outputs (I/O), a large number of electrode terminals (bumps) have come to be provided on the electrode terminal forming surface at higher density. Accordingly, electrode pads that are formed on a wiring board have come to be arranged at a very high density.
Wiring patterns for electrical connections to external connection terminals are connected to connection pads formed on the wring board. One end of each wiring pattern is located in an area (pad array area) where the connection pads are disposed in an area array or peripheral geometry, and the other end is located outside the pad array area. Therefore, wiring patterns to be connected to connection pads that are located in an inside portion of the pad array area need to be routed out so as to pass between connection pads.
However, when pad-interval between adjoining connection pads is small, the number of wiring patterns that can pass between adjoining connection pads is limited and hence the wiring patterns cannot be arranged so as to be connected to all connection pads in one wiring layer. This is because plural wiring layers 15 are layered, routable wiring patterns 14 are formed on each layer, and the connection pads 12 are electrically connected to external connection terminals IS through vias 16 (see FIG. 12).
The simplest routing method of the wiring patterns to be connected to the connection pads 12 is to route out wiring patterns 14 of each wiring layer 15 from each connection pad array loop in the pad array area in such a manner that the wiring layer 15 goes away from the semiconductor-element-side surface of the wiring board 10 as the corresponding loop goes inward starting from the outermost loop. However, this method has a problem in that the wiring patterns 14 cannot be routed out efficiently and the number of wiring layers 15 of the wiring board 10 becomes large.
As a method for solving the above problem, there is a method of periodically providing no-pad regions (i.e., regions where no pads are disposed) in an outer peripheral portion of a pad array area where connection pads are disposed in an area array geometry or a peripheral geometry. This method makes it possible to route out the wiring patterns efficiently from the pad array area and to thereby decrease the number of wiring layers of the wiring board.
To achieve the above pad geometry, it is necessary to design a semiconductor element so that its bumps are arranged to correspond to the geometry of the connection pads of the wiring board; for example, it is necessary to form, in an outer peripheral portion of a bump geometry area, no-bump regions (i.e., regions where no bumps are disposed) or electrodes that need not be connected to any connection pads of the wiring board (see e.g., JP-A-11-186332 and JP-A-2001-35950).
Incidentally, in semiconductor elements, the bump pitch is becoming increasingly small as the number of inputs and outputs increases. For example, consideration will be given to a relationship between the number of wiring patterns that can pass between adjoining connection pads and the bump pitch and the diameter of the connection pads to which the bumps are to be connected. Two 8-μm-wide wiring patterns can pass between adjoining connection pads when the bump pitch and the connection pad diameter are 110 μm and 70 μm, respectively, and one 8-μm-wide wiring pattern can pass between adjoining connection pads when the bump pitch and the connection pad diameter are 100 μm and 70 μm, respectively. And no 8-μm-wide wiring pattern can pass between adjoining connection pads when the bump pitch and the connection pad diameter are 90 μm and 70 μm respectively. In the last case, one wiring pattern comes to be able to pass between adjoining connection pads when its width is reduced to 6 μm.
However, in a manufacturing method of the related-art multilayer wiring board (build-up wiring board) which uses an organic material as a base material, it is very difficult to realize wiring patterns that are narrower than 8 μm. Under such a condition that no wiring pattern can pass between adjoining connection pads, wiring patterns can be routed out from only one outermost loop of the pad array area. Wiring patterns need to be routed out from the connection pads on the second outermost loop by using the next wiring layer, and so forth.
However, with increase in the number of wiring layers of a wiring board, there is a problem in that the production yield of the wiring board lowers. That is, in order to increase the production yield of a wiring board, it is advantageous to make the number of wiring layers of the wiring board as small as possible. As another method, it is thought to enable formation of narrower wiring patterns by increasing formation accuracy of the wiring pattern. However, this unavoidably increases the manufacturing cost Therefore, a designing method is desired which can decrease the number of wiring layers and increase the production yield of a wiring board while using the conventional manufacturing method, and which does not impose an excessive load on the layout of a semiconductor element.